There is a moment every power electronics engineer knows. You have just powered up your first motor controller PCB. The scope shows a beautiful sinusoidal phase voltage waveform. You connect a motor. The current waveform looks clean. You increase the duty cycle slowly.
At some point, something goes wrong. The FETs go into thermal runaway. The gate driver latches up. A ground bounce corrupts the current sense signal and sends the controller into a fault loop it cannot escape. Or worse: the board simply stops working with no obvious failure.
Motor controller PCB design is unforgiving. Every layout decision carries real consequences — for efficiency, for EMC, for thermal performance, for long-term reliability. This post covers the practices we have developed at Entlar over three generations of motor controller PCB design.
1. Power Path Layout: Current Loops Are Everything
The single most important concept in motor controller PCB layout is the current loop. Every switched current creates a time-varying magnetic field proportional to the rate of change of current (dI/dt) and the area of the current loop. That magnetic field induces voltage in adjacent circuits — that is EMC radiation and conducted interference.
Your job is to minimise the area of every high-frequency current loop.
The gate drive current loop: The gate driver sources and sinks current into the gate of each FET. This current path — from gate driver output, through the gate resistor, through the gate-source capacitance, and back to the gate driver return — must be as short as possible. Place gate resistors within 5 mm of the FET gate pin. Run the gate return directly back to the gate driver GND pin, not through the main power ground plane.
The switch node current loop: In a half-bridge, the switch node current commutates from the high-side FET to the low-side FET. The loop area is the sum of the drain-source area of the high-side FET, the commutation path to the bus capacitor, and back through the bus negative rail. Minimise this by placing the bus decoupling capacitors immediately adjacent to the FETs — within 10 mm if possible.
Practical rule: Sketch your current loops before you route your board. Identify the highest-frequency paths (switching transients at 10–100 kHz with 10–100 ns edges) and minimise their areas first.
2. Thermal Management: Design for the Worst Case
FET junction temperature is the primary reliability limiter in motor controllers. Every 10°C increase above 100°C roughly halves FET lifetime (due to electromigration and hot carrier injection). Design for the worst case: maximum ambient temperature (often 85°C for electronics), maximum continuous load current, minimum airflow.
Copper pours for thermal spreading: For surface-mount FETs, the PCB copper pour connected to the thermal pad is your primary heat path. Use the maximum number of vias allowed by your manufacturer to connect top-side copper to inner planes and bottom-side copper. A typical high-current FET pad might have 25–50 vias to the inner copper pour.
Thermal simulation before tape-out: Use your PCB design tool’s thermal simulator (Ansys Icepak integrated into Altium Designer, or KiCAD’s thermal analysis plugin) to estimate FET junction temperatures at maximum load before you send the board to fab. We found three layout iterations in simulation that would have caused field failures before we ever built a prototype.
Thermal interface material (TIM): If you are mounting to a heatsink or chassis, TIM selection matters. High-performance silicone-based TIMs (Bergquist GP1500, Fujipoly XR-m) offer 3–6 W/m·K conductivity versus 0.5–1 W/m·K for generic grey thermal paste. The difference in junction temperature can be 10–20°C at full load.
3. Current Sensing: Shunt vs. Hall vs. Isolated
Motor current sensing is required for FOC and for overcurrent protection. Three main approaches:
Shunt resistor (in-line or low-side): A small resistance (1–10 mΩ) in the current path. Differential voltage across it is amplified and sampled by an ADC. Low cost, high accuracy, no bandwidth limitation. Challenges: shunt power dissipation (at 10A and 5mΩ, that is 500 mW), common-mode rejection requirements, and placement constraints.
Hall-effect current sensor IC: A magnetically isolated current sensor (Allegro ACS series, Infineon TLE4971). High common-mode voltage tolerance, isolated output, BW typically 1–3 MHz. Higher cost and lower accuracy than a precision shunt.
Current sense amplifier + shunt: The Entlar approach. We use a 2 mΩ, 1% tolerance, low-inductance shunt (Isabellenhutte ISAS series) with a precision differential amplifier (INA240 from Texas Instruments, which has PWM rejection). The INA240’s PWM rejection feature is critical — it suppresses the switching noise that otherwise corrupts shunt measurements during PWM transitions.
Placement of shunt: For 3-phase FOC, you need current measurement on at least two phases. Options:
- Three shunts in the low-side FET source paths (simplest, most common)
- One shunt in the DC bus return (single-shunt method — requires careful timing)
- Two shunts with reconstruction of third phase from KCL
We use three low-side shunts. The ADC sample trigger is synchronised to the PWM carrier peak (centre of the switching period) to sample when switching noise is minimal.
4. Gate Drive: Slew Rate Is a Trade-Off
Gate drive design is fundamentally a trade-off between switching speed (efficiency, thermal performance) and EMC (dV/dt noise, conducted interference).
Faster switching (lower gate resistance, lower total gate charge FETs):
- ✅ Lower switching losses
- ❌ Higher dV/dt, more EMC issues
- ❌ Higher current spike through parasitic inductances → higher switch node ringing
Slower switching (higher gate resistance):
- ✅ Lower dV/dt, better EMC
- ❌ Higher switching losses
- ❌ Higher FET thermal dissipation
We tune our gate resistance in three steps:
- Start with the FET manufacturer’s recommended value (typically 4.7–10Ω for TO-263/TO-220 packages, lower for SMD packages)
- Measure switch node ringing with a scope and reduce gate resistance until ringing exceeds 10–15% of bus voltage
- Add a Schottky diode in anti-parallel with the turn-on gate resistor if you need asymmetric turn-on/turn-off slew rates
Bootstrap circuit care: For high-side FETs in non-isolated half-bridges, the gate drive voltage is typically generated by a bootstrap capacitor. Size this capacitor properly: C_boot ≥ Q_gate × 10 / ΔV_boot_max. Add a separate 100 nF ceramic capacitor in parallel for high-frequency bypass.
5. PCB Stack-Up for Motor Controllers
For a 3-phase motor controller handling 10–50A at 48V, we recommend a minimum 4-layer stack:
| Layer | Function |
|---|---|
| L1 (Top) | Component placement, high-current traces |
| L2 | Continuous ground plane (GND) |
| L3 | Continuous power plane or additional routing |
| L4 (Bottom) | Component placement, return paths |
The continuous L2 ground plane is not optional. It provides a low-impedance return path for every signal on L1, dramatically reducing ground noise and EMC radiation.
For mixed-signal boards (MCU + power stage on the same PCB), we add a split ground approach: separate copper pours for analog signal ground (AGND) and power ground (PGND), connected at a single star point near the power supply decoupling capacitor. This prevents power switching noise from coupling into the ADC reference.
6. EMC Design Rules
EMC compliance is not an afterthought — it is designed in. Our rules:
- Every high-dV/dt node (switch nodes, gate drive outputs) gets a small snubber capacitor (1–4.7 nF, placed immediately at the source) to limit radiated emissions
- All input power lines get a common-mode choke followed by differential-mode capacitors (X capacitors) before the bulk electrolytic
- Motor phase outputs get ferrite beads in series (300–600 mΩ at 100 MHz) to suppress conducted emissions on the motor cable
- Ground stitching vias around the board perimeter connect all layer ground planes
These are not theoretical. Our first prototype failed conducted emissions at 150 kHz (second harmonic of switching frequency). Adding 4.7 nF snubbers on the switch nodes and a common-mode choke on the input resolved the issue in one iteration.
Conclusion
Motor controller PCB design rewards precision, simulation, and iteration. The engineers who build reliable, efficient, EMC-compliant motor controllers are not the ones who are most creative — they are the ones who are most disciplined.
Minimise loop areas. Simulate thermal performance. Design gate drive slew rate as a deliberate choice. Build adequate prototypes. Test at thermal extremes.
The physics does not forgive corners that are cut.